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Semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors
Semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors
Integrated circuitry having adjacent electrically isolated field effect transistors is disclosed and which includes a bulk semiconductor substrate; an electrically insulative device isolation mass located on the substrate and positioned between opposing active area regions; a first pair of LDD diffusion regions associated with the active area and abutting against the electrically insulative device isolation mass; a pair of field effect transistors each being received within one active area; a second paid of LDD diffusion regions associated with the active area and abutting against each field effect transistor; and a pair of electrically conductive transistor source and drain diffusion regions which are respectively spaced from the insulative isolation mass and field effect transistor.
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