Recovery circuit having long hold time and phase range

摘要

An recovery circuit is described for recovering data from serially transmitted digital signals wherein a very long hold time and infinite phase range is desired. The recovery circuit includes a variable delay line, a data tracking phase-locked loop (PLL), a clock tracking phase- locked loop, a phase sensor, and a switch. The variable delay line is responsive to a feedback signal and a clock signal for generating a first delayed phase-locked signal. The data tracking phase-locked loop is responsive to the first delayed phase-locked signal and a data signal for producing a data phase error signal. Similarly, the clock tracking phase- locked loop is responsive to the clock signal for providing a second delayed phase-locked signal. Responsive to both of the delayed phase- locked signals is the phase sensor which provides a select output signal when the phase-locked signals are in phase with each other. The switching circuit is connected to the data phase error signal for asserting data phase error signal, in response to the select output signal, as the feedback signal to the variable delay.