首页>
外国专利>
EXPOSING METHOD OF CIRCUIT PATTERN OF CHIP-PERIPHERY PORTION, AND EXPOSING METHOD OF ALIGNMENT MARK, AND SEMICONDUCTOR-DEVICE MANUFACTURING METHOD USING THE EXPOSING METHOD
EXPOSING METHOD OF CIRCUIT PATTERN OF CHIP-PERIPHERY PORTION, AND EXPOSING METHOD OF ALIGNMENT MARK, AND SEMICONDUCTOR-DEVICE MANUFACTURING METHOD USING THE EXPOSING METHOD
展开▼
机译:芯片外围部分的电路图形的曝光方法,对准标记的曝光方法以及使用该曝光方法的半导体器件制造方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
PROBLEM TO BE SOLVED: To improve the drawing precision of an alignment mark and a circuit-pattern in a chip, by correcting respectively their proximity effect, and by forming the alignment mark apart from the end of the chip or the circuit-pattern in the chip by a distance not smaller than the tolerance distances of their proximity effect. ;SOLUTION: An exposure-oriented acceleration voltage of 100 kV is specified, and a distance δd between an alignment mark and a chip region is specified. Then, to a circuit-pattern 21 in the chip and to alignment marks 22, their proximity effect corrections are applied respectively to subject them to exposure. When making the distance δd equal to 80 μm or 65 μm, the influence of the proximity effect of the alignment marks and the circuit-pattern in the chip can be removed therefrom. Even when increasing the acceleration voltage of an electron beam for pattern formation, the proximity effect of the exposure circuit-pattern and the alignment marks can be corrected properly to make improvable the drawing precision of the fine circuit- pattern and the alignment marks. Therefore, the yield of a semiconductor-device manufacture can be removed to make securable its throughput.;COPYRIGHT: (C)2000,JPO
展开▼