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Component null in order conservation the integration MOS power transistor from voltage gradient

机译:为使积分MOS功率晶体管免受电压梯度影响,零组件应予保留

摘要

A voltage gradient protective device for a monolithic vertical power MOS (VDMOS) transistor and logic circuit component, in which the transistor drain is formed by the first conductivity type substrate (1, 2) and the logic components are formed in a second conductivity type surface well (10), comprises a resistor (40) in series with each of the first conductivity type regions (31) connected to the logic circuit earth or to a node of low impedance wrt. earth. Preferably, the other terminal of the resistor (40) is connected to an earth contact (32) on the well (10) and the resistor corresponds to a polysilicon region formed on a thick oxide layer (41).
机译:用于单片垂直功率MOS(VDMOS)晶体管和逻辑电路组件的电压梯度保护器件,其中晶体管漏极由第一导电类型衬底(1、2)形成,逻辑组件形成在第二导电类型表面阱(10)包括与每个第一导电类型区域(31)串联的电阻器(40),每个第一导电类型区域(31)连接到逻辑电路接地或低阻抗wrt的节点。地球。优选地,电阻器(40)的另一端子连接到阱(10)上的接地触点(32),并且电阻器对应于在厚氧化层(41)上形成的多晶硅区域。

著录项

  • 公开/公告号JP2980106B2

    专利类型

  • 公开/公告日1999-11-22

    原文格式PDF

  • 申请/专利权人 ESU TEE MIKUROEREKUTORONIKUSU SA;

    申请/专利号JP19980156872

  • 发明设计人 ANTOAANU PABURAN;PIETORO FUIKERA;JAN BARE;

    申请日1998-05-22

  • 分类号H01L29/78;H01L21/822;H01L21/8234;H01L27/04;H01L27/088;

  • 国家 JP

  • 入库时间 2022-08-22 01:58:09

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