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Component of protection of an integrated MOS power transistor against voltage gradients

机译:集成MOS功率晶体管的电压梯度保护组件

摘要

The present invention relate to a device of protection against voltage gradients of a monolithic component including a vertical MOS power transistor and logic circuits. The protection circuit has an N- type substrate corresponding to the drain of the MOS transistor, and logic components being realized in at least one P-type well formed in the upper surface of the substrate. Each of the N-type regions connected to the ground of the logic circuit, or to a node of low impedance with respect to the ground, is in series with a resistor.
机译:本发明涉及一种保护装置,以防止整体组件的电压梯度,该组件包括垂直MOS功率晶体管和逻辑电路。该保护电路具有与MOS晶体管的漏极相对应的N型衬底,并且在形成于该衬底的上表面中的至少一个P型阱中实现逻辑部件。连接至逻辑电路的接地或相对于接地的低阻抗节点的每个N型区域均与电阻串联。

著录项

  • 公开/公告号US6057577A

    专利类型

  • 公开/公告日2000-05-02

    原文格式PDF

  • 申请/专利权人 STMICROELECTRONICS S.A.;

    申请/专利号US19980085521

  • 发明设计人 JEAN BARRET;ANTOINE PAVLIN;PIETRO FICHERA;

    申请日1998-05-27

  • 分类号H01L23/62;H01L31/119;H01L29/76;

  • 国家 US

  • 入库时间 2022-08-22 01:37:16

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