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The semiconductor integrated circuit and its design manner and records the design program of the semiconductor integrated circuit the record media

机译:半导体集成电路及其设计方式和记录半导体集成电路的设计程序的记录介质

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for which a clock signal- generating circuit, etc., provided in the integrated circuit can be tested easily. ;SOLUTION: A select signal output circuit 10 is provided in a semiconductor integrated circuit. When '0' is inputted to the D-terminal of the circuit 10, the circuit 10 switches a selector 12 to a partial circuit 2 side and a scan FF(flip flop) 11 inputs the output of the partial circuit 2. At the time of conducting scan tests, a select signal of '0' or '1' value is inputted to the select signal output circuit 10 from a scan-in terminal 3 and further inputted to the selector 12. The selector 12 selects the partial circuit 2 side when the select signal is '0' or the clock signal of a clock signal generating circuit 9 when the select signal is '1'. The output of the partial circuit 2 or the clock signal of the clock signal generating circuit 9 inputted to the scan FF 11 is outputted to the outside from a scan-out terminal 8 through a scan path 20.;COPYRIGHT: (C)1999,JPO
机译:解决的问题:提供一种半导体集成电路,可以容易地测试集成电路中提供的时钟信号发生电路等。解决方案:在半导体集成电路中提供选择信号输出电路10。当将“ 0”输入到电路10的D端子时,电路10将选择器12切换到部分电路2侧,并且扫描FF(触发器)11输入部分电路2的输出。在进行扫描测试的过程中,选择值“ 0”或“ 1”从扫描输入端子3输入到选择信号输出电路10,并进一步输入到选择器12。选择器12选择部分电路2侧当选择信号为“0”或一个时钟信号生成电路9的时钟信号时,选择信号是“1”。输入到扫描FF 11的部分电路2的输出或时钟信号生成电路9的时钟信号通过扫描路径20从扫描输出端子8输出到外部。版权:(C)1999,日本特许厅

著录项

  • 公开/公告号JP2989586B2

    专利类型

  • 公开/公告日1999-12-13

    原文格式PDF

  • 申请/专利权人 MATSUSHITA DENKI SANGYO KK;

    申请/专利号JP19980203231

  • 发明设计人 TAKEOKA SADAMI;

    申请日1998-07-17

  • 分类号G01R31/28;G06F11/22;H01L21/822;H01L27/04;

  • 国家 JP

  • 入库时间 2022-08-22 01:58:05

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