Dual damascene structure for multilevel metallization and interconnect

摘要

A dual damascene structure comprises a dielectric layer (302, 402) on a semiconductor substrate (300, 400). First and second etch stop layers (306, 310) are formed on the dielectric layer with respective first and second openings at positions corresponding to each other. An interconnect is formed in the dielectric layer and etch stop layers. An Independent claim is also included for a method of forming the above dual damascene structure, comprising: (a) forming a dielectric layer above a semiconductor substrate; (b) forming a patterned mask layer on the dielectric layer; (c) a first implanting step to form a first etch stop layer in the dielectric layer, having an opening; (d) forming a spacer layer on the mask layer; (e) forming a patterned photoresist layer on the spacer layer; (f) removing parts of the photoresist and spacer layer to form a spacer on the sidewall of the mask layer and to leave the spacer layer under the photoresist layer; (g) a second implanting step to form a second etch stop layer in the dielectric layer, having a trench opening; (h) removing the spacer layer, spacer, and mask layer; (i) removing parts of the dielectric layer to expose parts of the substrate and etch stop layers; (j) forming a conductive layer (314, 414) on the substrate and etch stop layers; and (k) removing the conductive layer above the second etch stop layer to form the dual damascene structure.