METHOD OF FABRICATING A DUAL -DAMASCENE STRUCTURE IN AN INTEGRATED CIRTCUIT WITH MULTILEVEL-INTERCONNECT STRCTURE

摘要

A semiconductor fabrication method is provided for the fabrication of a dual-damascene structure in an integrated circuit with a multilevel-interconnect structure. This method is characterized in that, after the dual-damascene hole is formed, a conformal barrier/adhesive layer is first formed over all the sidewalls of the dual-damascene hole, but not filling the dual-damascene hole. An anisotropic etching process is then performed to etch away the part of the conformal barrier/adhesive layer that is laid at the bottom of the dual-damascene hole and subsequently the underlying part of the topping layer until exposing the metallization layer. Finally, a conductive material, such as copper, is deposited into the remaining void portion of the dual-damascene hole. The deposited conductive material and the remaining part of the conformal barrier/adhesive layer in the dual-damascene hole in combination constitute the intended dual-damascene structure. The conformal barrier/adhesive layer serves as a diffusion protective layer for the dielectric layers, which can subsequently help prevent diffusion of the spluttering metal atoms from the metallization layer during the RIE (Reaction Ion Etching) process into the dielectric layers.