Clock disturbance detection based on ratio of main clock and subclock periods

摘要

A bipolar-clock monitor circuit includes a first shift register (202, 302)) shifting positive-polarity pulse signal (SP) according to the negative-polarity pulse signal (SN) to produce a i-bit-shift signal and a j-bit-shift signal. The integers i and j are determined based on the period ratio of a main clock and a subclock included in the bipolar clock signal so that the i-bit-shift signal is identical with the j-bit-shift signal when the bipolar clock signal is normal. The non-coincidence determination circuit (203, 303) checks whether the i-bit-shift signal coincides with the j-bit-shift signal and produces a disturbance detection signal when the i-bit-shift signal does not coincide with the j-bit-shift signal.