A set of series-connected N-type MOSFETs (1,3) and a set of series-connected N-type MOSFETs (2,4) are connected in parallel to each other between the pull-up node (e1) and GND of the P-type MOSFET (5). do.;A set of series-connected P-type MOSFETs 11 and 13 and a set of series-connected P-type MOSFETs 12 and 14 are connected between the power supply line VDD and the pull-down node f1 of the N-type MOSFET 15. Are connected in parallel to each other. The pull-down node f1 is connected to the gate of the N-type MOSFET 16, and the pull-up node a1 is connected to the input gate of the inverter 17. The transition of the signal input to each transistor is detected to generate a pulse signal at the output OUT of the inverter. The gate signal b1 is delayed with respect to the gate signal a1 by one stage of the inverter, the gate signal c1 is delayed with respect to the gate signal a1 by three stages of the inverter, and the gate signal d1 is delayed by three stages of the inverter. It is delayed with respect to the gate signal b1. Thus, a signal with sufficient pulse width can be generated for the fine input pulse without extending the pulse width or waveform shaping at the front end.
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