MICROPROCESSOR ARCHITECTURE CAPABLE OF SUPPORTING MULTIPLE HETEROGENEOUS PROCESSORS

摘要

A computer system including a microprocessor architecture capable of supporting multiple processors includes a memory array unit (MAU), an MAU system bus including a data bus, an address bus and a control signal bus, and a data bus, an address bus and a control signal bus. It includes an I / O bus, a plurality of I / O devices, and a plurality of microprocessors. Data and command caches, data transfer between memory, and other I / O devices are handled using switch network port data and command caches and I / O interface circuitry. Access of the memory buses is controlled by an arbitration circuit using fixed and dynamic priority schemes. Test and set bypass circuits are provided to prevent memory band loss due to spin locking. The content addressing memory (CAM) stores the semaphore's address and is checked by devices attempting to access the memory to determine whether the memory is available before an address is loaded on the memory bus. Writing to an area protected by a semaphore clears the semaphore and CAM. The column match comparison circuit is provided to reduce the memory latency by giving increased priority in order to succeed in requesting access to memory areas having identical addresses. Dynamic switch / port coordination is provided by changing the device's unique priority of the devices, the number of serviced requests based on thermal match, the number of service rejections of the device, and the priority based on the number of serviced devices. Circuits are also provided for invalidation and interference so that the slave devices can operate with the latest information. Circuits are also included to provide dynamic memory refresh because each processor knows the lap time between when the memory refresh occurs and the refresh request.