CACHE COHERENCY CONTROLLER FOR SYSTEM HAVING DISTRIBUTED SHARED MEMORY STRUCTURE

摘要

PURPOSE: A controller for maintaining cache identifying of a system having a distribution memory structure is provided to prevent unnecessary snooping of processors in a node by using a cache identification maintaining protocol of a pull-map directory method and a multi-memory channel for enhancing of a performance of a system having a distribution sharing memory structure. CONSTITUTION: One node has a plurality of CPUs(CPU1¯CPUn), a distribution sharing memory(36) and a cache structure for supporting directory base identification maintenance. In addition, a CPU memory controller(35) and a node memory controller(37) for supporting a multi-memory channel, a system bus(S_BUS) for interactively connecting the CPU memory controller(35) and the node memory controller(37) and nodes therebetween and a CPU local bus(L_BUS) for connecting the CPUs(CPU1¯CPUn) to each section of a system are provided. In addition, a cache controller(31), an external cache memory(32), a directory cache controller(33), a system bus requesting and responding device(38) and a system bus interface unit(39) are provided.