Static semiconductor memory (SRAM) for LV operation with CMOS memory cells, each with six transistors of specified conductivities

摘要

The first four transistors (2b,a;3b,a) have each an active drain region (12a,12b,12i,12g), each two of opposite conductivity. The fifth transistor (1b) has a first active region (12d) of first conductivity, and a second active region (12e) electrically coupled to the first active drain region. A sixth transistor (1a) has a third active region (12a) of first conductivity, and fourth active region (12b) electrically coupled to the second active drain region. A common contact (14j,14k) is located at the side of an active drain region (12g,12i) of each of two load transistors (3a,b).