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Test system for multiple memory integrated circuit has device for sequential selection of test circuits and hence reduction in overall testing time
Test system for multiple memory integrated circuit has device for sequential selection of test circuits and hence reduction in overall testing time
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机译:用于多存储器集成电路的测试系统具有用于依次选择测试电路并因此减少总体测试时间的装置
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摘要
When test system is operating in write mode and data is being written to the memory devices the sample selection circuit selects all the memory devices so that groups of tested memory devices are sequentially selected and data is read from them. Test system has a pattern generator, a sample selection circuit and a report register circuit that captures signals from tested memory device is working correctly or not.
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