multiprozessorsystem with cache memory

摘要

A multiprocessor system having a multiplicity of serial system buses arranged in parallel is proposed to which a high number of system components (SPK1, SPKm, SSK) can be connected. The system components (SPK1, SPKm, SSK) are processor system components (SPK1, SPKm) exhibiting caches and memory-type system components. Each system component (SPK1, SPKm, SSK) is connected to each serial system bus. The processor-type system components (SPK1, SPKm) exhibit means for maintaining the consistency of the contents of the caches for each serial high-speed bus (SB1, SBn-1, SBn). IMAGE