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Single-poly EEPROM cell structure operations and array architecture
Single-poly EEPROM cell structure operations and array architecture
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机译:单多晶硅EEPROM单元结构操作和阵列架构
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摘要
A single-poly EEPROM cell comprising an inverter and a capacitive coupling area. The inverter is formed by: a p-well formed in a substrate; a gate structure formed atop the p-well and being formed from a thin gate oxide layer underneath a conductive layer; an n-base formed adjacent to a first edge of the gate structure and within the p-well; a p+ structure formed within the n-base; and a n+ structure adjacent a second edge of the gate structure and within the p-well. The capacitive coupling area is formed from a second p-well formed in the substrate and a floating gate, the floating gate formed from the conductive layer and capacitively coupled to the second p-well.
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