首页>
外国专利>
Clock synchronous semiconductor memory device capable of preventing outputting of invalid data
Clock synchronous semiconductor memory device capable of preventing outputting of invalid data
展开▼
机译:能够防止无效数据输出的时钟同步半导体存储装置
展开▼
页面导航
摘要
著录项
相似文献
摘要
A gate circuit is turned on in synchronization with an internal clock signal at a timing faster than activation of an output buffer circuit, and internal data is transmitted from the gate circuit to an output buffer circuit externally outputting data. Generation of an internal clock signal is stopped at a timing faster than deactivation of the output buffer circuit, and the gate circuit is set to the latching state. According such arrangement, output of invalid data is prevented.
展开▼