Method of extracting timing characteristic of transistor circuit, storage medium storing timing characteristic library, method of designing LSI, and gate extraction method

摘要

The present invention relates to a method of extracting timing characteristics from transistor circuit data of component design assets (such as a CPU core) such as a CPU core, and an extracted timing characteristic is a timing verification, logic synthesis or circuit of a circuit including a module to be extracted It is used for timing constraints in imine driven layout. In particular, when timing verification is performed by a simulation, the timing rule fitting condition of the module is included in the timing characteristic, so that verification without a pseudo error can be verified. The present invention relates to a structure of a timing characteristic library, a storage medium storing the same, and an LSI design method using the same.