首页> 外国专利> METHOD AND DEVICE FOR CALIBRATING PULSE WIDTH TIMING ERROR CORRECTION IN SEMICONDUCTOR INTEGRATED CIRCUIT TEST

METHOD AND DEVICE FOR CALIBRATING PULSE WIDTH TIMING ERROR CORRECTION IN SEMICONDUCTOR INTEGRATED CIRCUIT TEST

机译:半导体集成电路测试中脉宽定时误差校正的方法和装置

摘要

PROBLEM TO BE SOLVED: To provide a method and device for correcting a pulse width timing error while a high-performance integrated circuit device is being tested by an automatic testing device(ATE). ;SOLUTION: Two outputs are supplied to a driver format logic 82, and are supplied to a strobe format logic 84 after a reciprocating transmission delay. The OR logic operation of both of them is calculated by the logic circuits. By using two independent event sequencers A and B, a higher event speed is achieved. More specifically, the higher event speed is achieved by shifting one event sequencer from the other event sequencer by a slight value, namely a value that is smaller than the value of time that one sequencer spends for generating the repetition of a succeeding event. While one sequencer is outputting data, data is loaded into the other sequencer.;COPYRIGHT: (C)2001,JPO
机译:解决的问题:提供一种在自动测试装置(ATE)对高性能集成电路装置进行测试时校正脉冲宽度定时误差的方法和装置。解决方案:两个输出被提供给驱动器格式逻辑82,并且在往复的传输延迟之后被提供给选通格式逻辑84。两者的逻辑或运算由逻辑电路计算。通过使用两个独立的事件定序器A和B,可以实现更高的事件速度。更具体地,通过将​​一个事件定序器与另一事件定序器相移一个较小的值,即小于一个定序器用于生成后续事件的重复所花费的时间的值,来实现更高的事件速度。一个定序器正在输出数据时,数据被加载到另一个定序器中。; COPYRIGHT:(C)2001,JPO

著录项

  • 公开/公告号JP2001305197A

    专利类型

  • 公开/公告日2001-10-31

    原文格式PDF

  • 申请/专利权人 SCHLUMBERGER TECHNOL INC;

    申请/专利号JP20010067243

  • 发明设计人 HELLAND JOSEPH C;

    申请日2001-03-09

  • 分类号G01R31/3183;G01R31/28;G01R35/00;G11C29/00;

  • 国家 JP

  • 入库时间 2022-08-22 01:30:27

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