METHOD OF GENERATING R,C PARAMETERS CORRESPONDING TO STATISTICALLY WORST CASE INTERCONNECT DELAYS

摘要

A method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs, comprising the steps of: computing a statistically worst case interconnect delay from randomly generated material and property values (302, 303, 304, 305); computing a representative set of material and geometry values corresponding to the statistically worst interconnect delay (307); and computing R,C parameters corresponding to the statistically worst case interconnect delay from the representative set of material and geometry values (308).