Analytical and statistical interconnect delay models for VLSI system design.

摘要

Due to the reduction of transistor sizes and the increase in operating frequencies, interconnect delays are increasingly important in determining VLSI system performance. This has made the accurate estimation of interconnect delays essential for the design and fabrication of high performance VLSI. However, existing circuit simulators are too time-consuming for repeated use within iterative design optimizations. On the other hand, conventional closed form delay models are inaccurate.; This dissertation discusses interconnect delay models which approach simulation-based accuracy without compromising the delay calculation speed of closed form delay models. The first part of the dissertation deals with two pole based analytical delay models; the second part proposes HSPICE based statistical delay models.; First, we explore analytical delay models under ramp inputs. These models assume input voltage to be a ramp waveform, which is very close to the behavior of real voltage sources. In addition, two poles are used to increase the accuracy of the models. Second, we will discuss analytical delay models under step inputs. These models assume input voltage to be a step waveform, which is the same assumption as in the Elmore delay model. Introduction of Gramm-Schmidt-based approximation as well as the utilization of two poles enable new models to estimate interconnect delays far more accurately than the Elmore delay. Gramm-Schmidt-based approximation in conjunction with the two-pole method also leads to analytical delay models under ramp inputs. Finally, this dissertation proposes purely statistical delay models under ramp input. These models are created from multiple HSPICE simulator runs, and yield delay estimations that are very close to those of the HSPICE simulator while maintaining constant-time estimation costs.