Fabrication of VDMOS structure with reduced parasitic effects

摘要

A process for fabricating a VDMOS structure comprising the steps of forming a body region of a first conductivity type (p-) by implanting and diffusing a dopant (B) through a first aperture defined by the edges of a patterned gate conductor layer (4) on a dielectric gate layer (3) formed on the surface of an epitaxial layer (n). forming region (p+) with a higher dopant concentration within said body region (p-) by implanting dopant at a high kinetic energy down to a certain depth from the surface of the epitaxial layer, implanting and diffusing source regions of a second conductivity type (n+) in said body region (p-) projectively above said region of higher doping level (p+), comprises the following steps:forming a resist mask (Ms) defining apertures for implanting said source regions prior to the formation of said region (p+) of higher doping level:implanting through said resist mask (Ms), said dopant of a second conductivity type (n+) in a superficial zone of said body region (p-). and a dopant of said first conductivity type at a kinetic energy sufficient to implant the dopant (p+) at a depth below said superficial zone implanted with a dopant (n-) of the second conductivity type;annealing at a temperature and for a time sufficient to form (n+) source/ (p-) body junctions above body regions (p+) of a relatively high dopant concentration (p+).;An effective reduction of the gain of the parasite transistor is achieved without the need of a dedicated masking step.