Fabrication of VDMOS structure with reduced parasitic effects

摘要

A process for forming a vertical double-diffused metal oxide semiconductor (VDMOS) structure comprising a semiconductor substrate, an epitaxial layer on the substrate, and a dielectric gate layer on the epitaxial layer includes implanting a first concentration dopant of a first conductivity type through an aperture defined by edges of a patterned gate conductor layer on the dielectric gate layer so that the first concentration dopant diffuses to form a body region of the VDMOS structure. A mask is formed on the patterned gate conductor layer and on a first portion of the body region for defining apertures exposing second portions of the body region. The process includes implanting through the apertures of the mask a dopant of a second conductivity type into the body region so that the dopant diffuses to define source regions therein, and implanting through the apertures of the mask a second concentration dopant of the first conductivity type so that the second concentration dopant is implanted at a depth below the source regions to form regions with a higher dopant concentration within the body region. The process further includes annealing to form source and body junctions above the higher dopant concentration regions within the body region.