Network for transferring consecutive packets between processor and memory with a reduced blocking time

摘要

For making in a parallel computer system an interconnection network transfer data sequences, each composed of consecutive packets, from input ports (17) to a destination port indicated among output ports (19) by a routing address specified by a leading packet of each data sequence, control registers (31) hold the routing address of a privileged sequence determined by arbiters (39) in response to such addresses held in the control registers and stored in control buffers (33). Data of the consecutive packets of the privileged sequence are simultaneously stored in and produced from data buffers (37). Controlled by the arbiters, input selectors (41, 43) select the data for delivery to the destination port through output buffers (55) and output selectors (57) controlled by a selector operating arrangement (59-63). When the data of the consecutive packets are not yet wholly stored in the data buffers, the input selectors select only those already stored in the data buffers and then select the data of remaining ones of the consecutive packets as soon as they reach the data buffers.