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- Low Voltage Dual-Well MOS Device Having Ruggedness Low On-Resistance and Improved Body Diode Reverse Recovery

机译:-具有坚固性低的导通电阻和改进的体二极管反向恢复的低压双阱MOS器件

摘要

PURPOSE: A low-voltage MOS device is provided to obtain high durability and low resistance and to improve main body diode reverse recovery characteristic. CONSTITUTION: An upper layer(102) doped lightly into an N-type is formed on a single-crystal silicon substrate(101), and a further a blanket(103) doped heavily in N-type is made. An insulating layer(106) and a conductive layer(107) are stacked as a gate(105), and each layer is doped in the order of N-type and P-type from an opening (110) to fuse itself with the blanket(103), thus an N-well(108), a P-well(109), and under the gate(105), an N neck region(111) are made. Next, a P-well(112) and an N-source(113) are made by the implantation of P-type and N-type dopant, and a dielectric film(115) and a source metal(114) are deposited. As a result, a parasitic BJT function made of the junction of the N+-source, the P-well, and the N-well/the N-epitaxial layer is reinforced, and the electron diffusing current in the P-well increases, and minority charges accumulated in the N-epitaxial layer and the P-well decrease.
机译:目的:提供一种低压MOS器件,以获得高耐用性和低电阻并改善主体二极管的反向恢复特性。组成:在单晶硅衬底(101)上形成轻掺杂为N型的上层(102),再制得一层重掺杂为N型的覆盖层(103)。绝缘层(106)和导电层(107)被堆叠为栅极(105),并且每层从开口(110)以N型和P型的顺序掺杂,以使其自身与毯子融合。 (103)形成N阱(108),P阱(109),在栅极(105)的下方形成N颈区域(111)。接下来,通过注入P型和N型掺杂剂来制造P阱(112)和N源(113),并且沉积介电膜(115)和源极金属(114)。结果,增强了由N +源,P阱和N阱/ N外延层的结构成的寄生BJT功能,并且P阱中的电子扩散电流增加,并且在N外延层和P阱中积累的少数电荷减少。

著录项

  • 公开/公告号KR20010007229A

    专利类型

  • 公开/公告日2001-01-26

    原文格式PDF

  • 申请/专利权人 INTERSIL CORPORATION;

    申请/专利号KR20000030639

  • 发明设计人 ZENG JUN;WHEATLEY JR CARL FRANKLIN;

    申请日2000-06-03

  • 分类号H01L29/772;

  • 国家 KR

  • 入库时间 2022-08-22 01:14:17

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