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Circuit arrangement and method for testing of logic combinational circuits
Circuit arrangement and method for testing of logic combinational circuits
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机译:用于测试逻辑组合电路的电路装置和方法
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摘要
The circuit arrangement is provided to test at least one logic circuit network (TB1,TBn). The circuit arrangement may have a test pattern generator (TMG) for generating test patterns which are applied to the inputs of the network. A test response analysis unit (TA) analyses the test responses output from the switch network. A test unit (TS) is also provided. During a test cycle, the test control unit (TS) disconnects each switch network to be tested from the other networks. The length of the test pattern output from the test pattern generator is set according to the number of inputs of the test network being tested.
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