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Digital circuit with boundary scan cell with memory unit ensures that digital units can be tested without electrical access, with control and observation of signal connections
Digital circuit with boundary scan cell with memory unit ensures that digital units can be tested without electrical access, with control and observation of signal connections
The digital circuit has at least one boundary scan input cell (BSE) and at least one boundary scan output cell (BSA) with a memory unit (SP) between them that is connected to an output of a flip-flop unit (FFE) in the boundary scan input cell and an input of the boundary scan output cell. The memory unit is a shift register or memory cells of an SRAM.
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