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Phase-locked loop or delay-locked loop circuitry for programmable logic devices
Phase-locked loop or delay-locked loop circuitry for programmable logic devices
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机译:可编程逻辑器件的锁相环或延迟锁相环电路
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摘要
A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.
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