Manufacturing process for non-volatile floating gate memory cells integrated on a semiconductor substrate and comprised in a cell matrix with an associated control circuitry

摘要

A process for forming floating gate non-volatile memory cells in a cell matrix with associated control circuitry comprising both N-channel and P-channel MOS transistors is provided. The process includes forming active areas in a substrate for the cell matrix and the associated control circuitry. A first thin oxide layer and a first polysilicon layer are deposited on the active areas to produce floating gate regions of the memory cells, and a second dielectric layer is deposited on the active areas. A second polysilicon layer is then deposited on the active areas. A masking and etching step is performed for exposing the substrate for the associated control circuitry followed by the deposition of a third polysilicon layer. The third polysilicon layer is defined to produce the gate regions of the transistors for the associated control circuitry while the third polysilicon layer is removed from the cell matrix. A self-aligned etching step is performed to define the gate regions of the memory cells, and dopants are implanted in the junction areas to produce the source/drain regions of the memory cells.