Ultra short transistor channel length formed using a gate dielectric having a relatively high dielectric constant

摘要

An integrated circuit fabrication process is provided for forming a transistor in which the channel length is mandated by the width of a gate conductor formed upon a gate dielectric having a dielectric constant greater than about 3.8. The thickness of the gate dielectric may be made sufficiently large to serve as a mask during subsequent implantation of impurities into a substrate. The gate conductor and the gate dielectric are first patterned using lithography and an etch step. In one embodiment, a masking layer is then formed across a select portion of the gate conductor and an ensuing source region of the substrate. The uncovered portion of the gate conductor is etched to expose a region of the gate dielectric. A first implant of impurities is forwarded into regions of the substrate not covered by the masking layer to form an LDD area underneath the exposed region of the gate dielectric and a heavily doped drain region laterally adjacent the LDD area. A second implant is then forwarded into the source region to form a heavily doped source region. In another embodiment, the masking layer used to originally pattern the gate conductor is etched to expose portions of the gate conductor. Those exposed portions are then removed. A single implant of impurities is forwarded into the substrate exclusive of underneath the gate conductor. LDD areas are thusly formed beneath portions of the gate dielectric not covered by the gate conductor, and source/drain regions are formed laterally adjacent the LDD areas.