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Voltage-controlled delay line, direct phase controlled voltage- controlled oscillator, clock/data recovery circuit, and clock/data recovery apparatus
Voltage-controlled delay line, direct phase controlled voltage- controlled oscillator, clock/data recovery circuit, and clock/data recovery apparatus
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机译:压控延迟线,直接相控压控振荡器,时钟/数据恢复电路和时钟/数据恢复设备
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摘要
A clock/data recovery device employs a phase-locked loop that supplies a single clock signal and a control voltage signal to at least one clock/data recovery circuit. The clock/data recovery circuit has a voltage-controlled delay line or direct phase controlled voltage- controlled oscillator that generates a multiple-phase clock signal, which is used to recover a clock signal and data from a received data signal. The voltage-controlled delay line or direct phase controlled vottage- controlled oscillator has a cascade or ring of voltage controlled logic gates, with propagation delays controlled by the control voltage signal from the phase-locked loop, and additional logic gates that supply the clock signal from the phase-locked loop to a selectable one of the voltage-controlled logic gates.
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