A 3.125-Gb/s Burst-Mode Clock and Data Recovery Circuit With A Data-Injection Oscillator Using Half Rate Clock Techniques

摘要

In this paper, a burst-mode clock and data recovery (CDR) circuit using a half-rate clock technique is realized for optical communication. The CDR circuit contains a frequency detector and a data-injection oscillator to control the frequency of the recovered clock. In-lock operation can be accomplished on the first data transition, and then the output clock is in phase for all data until the data transition is over. The CDR circuit is implemented with TSMC 0.18-um 1P6M CMOS technology. The simulation results show that the proposed CDR circuit recovers the incoming data.