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CMOS output buffer with negative feedback dynamic-drive control and dual P,N active-termination transmission gates

机译:具有负反馈动态驱动控制和双P,N有源端接传输门的CMOS输出缓冲器

摘要

An output buffer for a line driver uses transmission gates for active termination. A large p-channel driver is pulsed on during a low-to-high output transition, but this driver is turned off once the output voltage reaches a threshold. A feedback circuit includes a sensing inverter that has its input connected to the output node. The sensing inverter causes the gate of the p-channel driver to be driven high once the output swings past the threshold. A similar n-channel driver transistor is pulsed on during a low-going output transition but is disabled by a feedback circuit that senses the output voltage falling below a threshold. A pullup transmission gate is also connected between the output and the power supply, while a pulldown transmission gate is connected between the output and ground. Each transmission gate contains a p-channel and a n-channel transistor in parallel. The sizes of the p-channel and n-channel transistors in the transmission gate is sufficiently small to provide a resistance of 25 to 30 ohms. Both transistors in the pullup transmission gate are turned on when the output is driven high, while both transistors of the pulldown transmission gate are turned on when the output is driven low. Having both n and p transistors of the transmission gate on provides a more linear resistance across the voltage swing of the output. Since termination of about 25-30 ohms is provided by the transmission gate, an external series resistor is not needed for dampening. When driving large capacitive loads, several nanoseconds of R-C delay can be saved.
机译:线路驱动器的输出缓冲器使用传输门进行有源端接。在从低到高的输出跳变期间,将触发一个大的p通道驱动器,但是一旦输出电压达到阈值,该驱动器就会关闭。反馈电路包括感测反相器,该感测反相器的输入连接至输出节点。一旦输出摆幅超过阈值,感应反相器就会将p通道驱动器的栅极驱动为高电平。相似的n沟道驱动器晶体管在低端输出转换期间被导通,但被反馈电路禁用,该反馈电路检测到输出电压降至阈值以下。上拉传输门也连接在输出和电源之间,而下拉传输门连接在输出和地之间。每个传输门包含一个并行的p沟道和n沟道晶体管。传输门中的p沟道和n沟道晶体管的尺寸足够小,可以提供25到30欧姆的电阻。当输出被驱动为高电平时,上拉传输门的两个晶体管都导通,而当输出被驱动为低电平时,下拉传输门的两个晶体管都被导通。传输门的n和p晶体管同时导通可在输出电压摆幅上提供更大的线性电阻。由于传输门提供了约25-30欧姆的端接,因此不需要外部串联电阻来进行阻尼。当驱动大容性负载时,可以节省几纳秒的R-C延迟。

著录项

  • 公开/公告号US6184730B1

    专利类型

  • 公开/公告日2001-02-06

    原文格式PDF

  • 申请/专利权人 PERICOM SEMICONDUCTOR CORP.;

    申请/专利号US19990432368

  • 发明设计人 KWONG DAVID;CHEN BAOHUA;

    申请日1999-11-03

  • 分类号H03B1/00;H03K3/00;

  • 国家 US

  • 入库时间 2022-08-22 01:05:20

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