Memory device wherein the number of columns equals the number of data bits transferred in parallel to/from the memory device

摘要

A data processing device comprising a processing device for processing data bits and a memory device, wherein the memory device and processing device are provided on the same semiconductor substrate. The memory device comprises a plurality of bitlines 7 and plurality of wordlines 9 arrange to form an array and a plurality of memory cells associated with the wordlines and bitlines. A plurality of sense amplifiers 13 are provided, each sense amplifier connected to a pair of associated bitlines, (or a bitline and a reference voltage), the associated pairs of bitlines forming a column C1 - Cn. The memory device is arranged such that the number of columns, and therefore the number of sense amplifiers, is equal to the number of the data bits transferred in parallel from the memory device. The memory device may be an embedded DRAM.