Article for de-embedding parasitics in integrated circuits

摘要

An article for de-embedding parasitics and/or acting as an on-wafer calibration standard is disclosed. In particular, some articles in accordance with the present invention provide structures on integrated circuits that mitigate the severity of parasitics Furthermore, some articles in accordance with the present invention are well-suited for use with conductive substrates that operate at high frequencies.;In an illustrative embodiment, conductive elements are used to construct structures near and/or around the leads on the integrated circuit. When the structures are grounded, the structures function to (at least) partially shield the leads to and from the DUT in a manner that is analogous to stripline, microstrip and coaxial cable. Because the electric fields emanating from the leads terminate in the grounded structure and not in the conductive substrate of the integrated circuit, the severity of the parasitics in the leads in mitigated.;An illustrative embodiment of the present invention is an integrated circuit comprising: a first pad, a first lead, a second pad, and a second lead made from a first conductive layer; a substrate; a first plate made from a second conductive layer that is between and electrically insulated from the first lead and the substrate; and a second plate made from the second conductive layer that is between and electrically insulated from the second lead and the substrate.