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Composite planarizing dielectric layer employing high density plasma chemical vapor deposited (HDP-CVD) underlayer
Composite planarizing dielectric layer employing high density plasma chemical vapor deposited (HDP-CVD) underlayer
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机译:使用高密度等离子体化学气相沉积(HDP-CVD)底层的复合平面化介电层
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摘要
A method for forming upon a substrate employed within a microelectronics fabrication a composite dielectric layer having etched via contact holes in which via poisoning is attenuated. There is provided a substrate employed within a microelectronics fabrication. There is formed upon the substrate a patterned microelectronics layer. There is then formed upon the substrate a blanket silicon containing dielectric layer employing high density plasma chemical vapor deposition (HDP-CVD). There is then formed upon the blanket silicon containing glass dielectric layer a low dielectric constant dielectric layer over which is formed a silicon oxide dielectric cap layer to form a composite inter-level metal dielectric (IMD) layer. There is then etched through the composite IMD dielectric layer a series of via contact holes. The method of formation, surface profile and properties of the blanket silicon containing glass dielectric layer provides attenuated via poisoning after via hole etching.
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