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MOS transistor with high-K spacer designed for ultra-large-scale integration
MOS transistor with high-K spacer designed for ultra-large-scale integration
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机译:具有高K隔离层的MOS晶体管专为超大规模集成而设计
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摘要
A MOS transistor having a source and drain extension that are less than 40 nanometers in thickness to minimize the short channel effect. A gate includes a high-K dielectric spacer layer to create depletion regions in the substrate which form the drain and source extensions.
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