SEMICONDUCTOR MEMORY WHICH CAN PERFORM MULTI-ROW ADDRESS TEST, AND ITS TEST METHOD

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which normal word lines and spare word lines can be normally enabled during a test driving successively many word lines in one instruction.;SOLUTION: This device is provided with a normal memory cell block having normal word lines electrically connected, a spare memory cell block having spare word lines electrically connected, a normal word line drive electrically connected to the normal word lines, and a spare word line driver electrically connected to the spare word lines, this spare word line driver is provided with a programmable address decoder generating a spare word line driver enable- signal on an enable-signal line, and a spare word line driver enable-signal pre- charge section responding to a multi-row address signal and connected electrically to the enable-signal line. Thereby, when a memory cell is tested driving successively many word lines, normal word lines and spare word lines can be normally enabled.;COPYRIGHT: (C)2002,JPO