HIGH SPEED SAMPLE-AND-HOLD CIRCUIT, AND CIRCUIT FOR REDUCING TIMING MISMATCHING IN HIGH SPEED PARALLEL CONNECTION SAMPLE-AND-HOLD CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a high speed sample-and-hold circuit including plural sample-and-hold circuits connected in parallel between an input and an output. SOLUTION: This circuit comprises a correcting circuit 104 connected to plural sample-and-hold sub-circuits 102a-102d, the correcting circuit can operate so that timing relation between a hold-signal and a clock signal is established for each of plural sample-and-hold sub-circuits being the same generally. Unsuccessful timing between plural sample-and-hold sub-circuits and distortion due to it are reduced by established timing relation. A method for reducing the unsuccessful timing in a high speed parallel connection sample-and-hold circuit is such that a hold-signal is synchronized with a clock signal by correcting a hold-signal for each of plural sample-and-hold sub-circuits in the sample-and- hold circuit and corrected hold-signals are utilized respectively in the sample- and-hold sub-circuit.