首页> 外国专利> Method of fabricating a semiconductor device using two chemical mechanical polishing processes to polish regions having different conductive pattern densities

Method of fabricating a semiconductor device using two chemical mechanical polishing processes to polish regions having different conductive pattern densities

机译:使用两种化学机械抛光工艺来抛光具有不同导电图案密度的区域的半导体器件的制造方法

摘要

A method of manufacturing a semiconductor device is capable of preventing a dishing phenomenon from occurring without using dummy patterns. A plurality of conductive patterns are formed along the entire surface of a semiconductor substrate with an irregular pattern density. The conductive patterns have a first stopper layer at the top thereof. An interlayer insulating layer is formed on the conductive patterns. Next, a second stopper layer is formed on the interlayer insulating layer. An etching mask is formed on the second stopper layer so as to expose a first region having a conductive pattern density that is higher than that of another region(s). By using the etching mask, the second stopper layer and part of the interlayer insulating layer are etched at the first region. The resultant structure is then first polished to expose the first stopper layer at the first region, by using a slurry that provides a polishing rate for the interlayer insulating layer that is higher than that for either the first and second stopper layers. The resultant structure is then polished for a second time to remove the second stopper layer form the region(s) of lower pattern density, by using a slurry that provides a polishing rate that is higher for the second stopper layer than for either the first stopper layer and the interlayer insulating layer.
机译:制造半导体器件的方法能够防止不使用虚设图案而发生凹陷现象。沿着半导体衬底的整个表面以不规则的图案密度形成多个导电图案。导电图案在其顶部具有第一停止层。在导电图案上形成层间绝缘层。接下来,在层间绝缘层上形成第二停止层。蚀刻掩模形成在第二停止层上,以暴露具有比其他区域高的导电图案密度的第一区域。通过使用蚀刻掩模,在第一区域蚀刻第二停止层和部分层间绝缘层。然后,通过使用浆料来对所得结构进行第一抛光,以在第一区域处暴露第一阻挡层,该浆料为层间绝缘层提供的抛光速率高于第一和第二阻挡层的抛光速率。然后第二次抛光所得结构,方法是使用一种浆料,该浆料对第二塞子层的抛光速率高于对第一塞子的抛光速率,从而从图案密度较低的区域去除第二塞子层。层和层间绝缘层。

著录项

  • 公开/公告号US2002132492A1

    专利类型

  • 公开/公告日2002-09-19

    原文格式PDF

  • 申请/专利权人 KIM JUNG-YUP;HAH SANG-ROK;

    申请/专利号US20020094994

  • 发明设计人 JUNG-YUP KIM;SANG-ROK HAH;

    申请日2002-03-12

  • 分类号H01L21/302;H01L21/461;

  • 国家 US

  • 入库时间 2022-08-22 00:53:03

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