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Semiconductor memory device with efficient and reliable redundancy processing
Semiconductor memory device with efficient and reliable redundancy processing
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机译:具有高效可靠的冗余处理的半导体存储设备
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摘要
A semiconductor memory device includes a data buffer for inputting/outputting data from/to an exterior of the device, a plurality of DRAM cell array blocks, an SRAM redundancy cell which is situated around each of the plurality of DRAM cell array blocks, a fuse circuit which stores therein an address of a defect memory cell in the DRAM cell array blocks, a comparison circuit which compares an input address with the address stored in the fuse circuit, and an I/O bus which couple the SRAM redundancy cell to the data buffer in response to an address match found by the comparison circuit.
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