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Methods of fabricating a scalable split-gate flash memory device having embedded triple-sides erase cathodes
Methods of fabricating a scalable split-gate flash memory device having embedded triple-sides erase cathodes
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机译:具有嵌入式三侧擦除阴极的可伸缩分裂栅闪存器件的制造方法
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摘要
A high-density, high-speed, low-power, scalable split-gate memory device and its fabrication are disclosed. The channel length of a control-gate device and the channel length of a floating-gate device in a split-gate flash memory device can be tailored separately to have a dimension much smaller than the minimum feature size of technology used. A sidewall erase cathode using a thin polycrystalline-silicon layer as the floating gate may be implemented. The sidewall erase cathode may be implemented on two advanced high-density isolation structures having embedded double-sides erase cathodes and high coupling ratio to form triple-sides erase cathodes, which provide high-efficiency, self-limiting erasing from the floating gate to the control gate. Moreover, self-aligned silicidation is applied to the control gate, the source/common buried source, and the drain of the device to reduce contact and interconnect resistances. Self-aligned contacts are formed by using silicon-nitride spacers on the sidewalls to reduce the space of contacts.
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