The invention includes several aspects related to semiconductor-on-insulator transistors, to memory and other DRAM circuitry and arrays, to transistor gate arrays, and to methods of fabricating such constructions. In one aspect, a semiconductor-on-insulator transistor includes, a) an insulator layer; b) a layer of semiconductor material over the insulator layer; c) a transistor gate provided within the semiconductor material layer; and d) an outer elevation source/drain diffusion region and an inner elevation diffusion region provided within the semiconductor material layer in operable proximity to the transistor gate. In another aspect, DRAM circuitry includes a plurality of memory cells not requiring sequential access, at least a portion of the plurality having more than two memory cells for a single bit line contact. In still another aspect, a DRAM array of memory cells comprises a plurality of wordlines, source regions, drain regions, bit lines in electrical connection with the drain regions, and storage capacitors in electrical connection with the source regions; at least two drain regions of different memory cells being interconnected with one another beneath one of the wordlines. In yet another aspect, a DRAM array has more than two memory cells for a single bit line contact, and a plurality of individual memory cells occupy a surface area of less than or equal to 2f(2ff/N), where f is the minimum photolithographic feature size with which the array was fabricated, and N is the number of memory cells per single bit line contact within the portion.
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