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Method and apparatus for measuring effects of packaging stresses of common IC electrical performance parameters at wafer sort

机译:在晶片分类时测量通用集成电路电气性能参数的封装应力影响的方法和装置

摘要

In the testing of one or more die as part of a semiconductor wafer, electrical testing of an unstressed die of a wafer is undertaken. The die of the wafer is then physically stressed to a first stressed state, and electrical testing is undertaken thereon. The die of the wafer is then physically stressed to a second stressed state, and electrical testing is again undertaken on the die as it is in its second stressed state. The results of the tests are compared and extrapolated to indicate electrical performance of the die in other physically stressed states. A relatively simple tool is provided for use in performing in this method in an effective and rapid manner.
机译:在测试作为半导体晶片一部分的一个或多个管芯时,对晶片的无应力管芯进行电气测试。然后,将晶片的裸片物理地施加应力到第一应力状态,并在其上进行电测试。然后,将晶片的裸片物理地施加应力到第二应力状态,并且当其处于其第二应力状态时,再次对裸片进行电测试。对测试结果进行比较和推断,以表明在其他物理应力状态下芯片的电性能。提供了一种相对简单的工具,用于以有效和快速的方式执行该方法。

著录项

  • 公开/公告号US6461879B1

    专利类型

  • 公开/公告日2002-10-08

    原文格式PDF

  • 申请/专利权人 ADVANCED MICRO DEVICES INC.;

    申请/专利号US20010757118

  • 发明设计人 SIDHARTH;RICHARD C. BLISH II;

    申请日2001-01-09

  • 分类号H01L216/60;G01R312/60;

  • 国家 US

  • 入库时间 2022-08-22 00:47:06

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