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2 OVERLAY REGISTRATION ERROR MEASUREMENT MADE SIMULTANEOUSLY FOR MORE THAN TWO SEMICONDUCTOR WAFER LAYERS
2 OVERLAY REGISTRATION ERROR MEASUREMENT MADE SIMULTANEOUSLY FOR MORE THAN TWO SEMICONDUCTOR WAFER LAYERS
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机译:2个以上两个半导体晶圆层同时进行的重叠配准误差测量
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摘要
PURPOSE: A method and an apparatus are provided to improve the technique for simultaneously measuring a registration error for overlaying semiconductor layers. CONSTITUTION: At least first, second, and third layers are formed on top of another. A first pattern is provided at a prescribed position of the first layer. A second pattern is provided at a prescribed position of the second layer and has a specific shape and a specific size and further has at least one discontinuous part formed at a predetermined position. A third pattern is provided at a prescribed position of the third layer and has a specific shape and the specific size of the second pattern, and further has at least one discontinuous part formed at its predetermined position; and the respective parts of the second and third patterns match with at least one discontinuous part of the other, when the second and third layers are registered.
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