PURPOSE: Even if same memory block is simultaneously accessed by a plurality of ports, a BUSY state is not generated because the internal memory can attend to consecutive and continuous processing at double the speed. CONSTITUTION: At timing(C1) of an external command cycle relevant to the A port, a Read command is entered at the A port. Further, at timing(C1') of an external command cycle relevant to the B port, a Read command is entered at the B port. Since timing of the Read command of the A port is slightly earlier, this Read command is performed ahead of the Read command entered at the B port Here, one external command cycle corresponds to four clock cycles. Each Read command is executed and completed in two clock cycles that correspond to one core operation cycle. Accordingly, in response to the Read commands entered at the A port and the B port at the intervals of four clock cycles that are equivalent to one external command cycle, read operations can be performed without generating a BUSY state even if the read access from the A port and the read access from the B port are directed to the same block. This is achieved by carrying out and completing each access in two clock cycles.
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