An Electrical Isolation Method for Single-Crystalline Silicon MEMS Using Localized SOI Structure

摘要

PURPOSE: An insulation method for single crystal silicon microelectromechanical system(MEMS) using selective silicon on chip structure is provided to reduce the quantity of a buried insulation layer and control the depth and thickness of the layer as compared with that using SOI wafer. CONSTITUTION: An etching hole is patterned on the electrode formed on a silicon substrate, and then the depth of buried insulation layer is defined by Reactive Ion Etching(RIE). According to standard SBM process, a protection layer is deposited along the sidewall within a hole and the bottom line of the electrode is etched horizontally. The protection layer and etching mask are removed and insulation material is filled up in the gap between the floating electrode and the substrate. By performing another SBM process, the electrode of final product is supported by the buried insulation layer and by which, electrically insulated structure from the substrate is formed.