Delay Locked Loop having a fast locking time

摘要

The invention initially using a second delay line having a delay locked loop, a first delay line with a minimum of delay, with more specifically, the delay line a large delay relates to a (DLL, Delay Locked Loop) in the semiconductor memory device, of the locking (locking) was faster time to generate a signal having a pulse width corresponding to the clock cycle of two times, to a method that can operate at high frequency. According to the invention To this end, the delay lock loop of the semiconductor memory device, comprising: a clock buffer to generate a level signal used internally receives the external clock; It is composed of a relatively large unit delay part 1 delay line for delaying the output signal of the clock buffer; Part 2 for delay line consists of a minimum delay unit to delay an output signal from the first delay line section; Delay lock loop drive signal to output to buffer the output signals from the second delay line section; Wherein each four clock in response to the output of the clock buffer in synchronism with every clock having a pulse width corresponding to the clock cycle of twice the first signal (ref) and a clock divider for generating a second signal (delay_in); The second signal by the first delay line section and the second delay modeling unit for generating the feedback signal to model the delay values ​​through the second delay line; A first phase comparator and second phase comparator for comparing the time difference between the two signals in response to said feedback signal and said first signal; First shifting means in response to an output signal of said first phase comparator for controlling the first delay line section delay value; And the second is characterized in response to an output signal of the second phase comparator formed by a second shifting means for controlling the second delay line unit delay value.