REGISTER CONTROLLED DELAY LOCKED LOOP REDUCED IN DELAYED LOCKING TIME, ESPECIALLY SHIFTING MANY STEPS WITH UNIT DELAY AT ONE TIME

摘要

PURPOSE: A register controlled delay locked loop(DLL) reduced in a delayed locking time is provided to prevent the wrong operation of the semiconductor chip by drastically reducing the setting time of the register controlled DLL. CONSTITUTION: A register controlled delay locked loop reduced in a delayed locking time includes a phase comparison unit, a shift register controller and a shift register. The shift register is provided with a latch, a delay selection signal generation unit and a switching unit. The latch is provided with a positive output terminal and a negative output terminal. The delay selection signal generation unit generates a delay selection signal corresponding to the corresponding stage in response to the latch values of the corresponding stage and the previous stage. And, the switching unit supplies the first and the second discharge paths to selectively discharge the positive output terminal and the negative output terminal of the corresponding stage controlled by the odd/even acceleration shift register control signal, the odd/even normal shift control signal and the latch value of the adjacent stage.