A register controlled delay locked loop using a TDC and a new fine delay line scheme

摘要

This paper presents a register controlled delay lock loop (RCDLL) with a time-to-digital converter (TDC) and a new fine delay line (FDL) scheme. The architecture of the proposed DLL uses a time-to-digital converter (TDC), a digital-to-time converter (DTC) scheme for short length of coarse delay line (CDL), and a open loop duty cycle corrector (DCC). While the conventional DLL has two feedback loops, the DLL with an open loop DCC has only one loop. So, it occupies a small area compared to the conventional one. Moreover, new FDL scheme is proposed which is capable of seamless boundary switching with a fixed delay step. HSPICE simulation results are based with ANAM 0.18/spl mu/m 1P6M CMOS process with 1.5V power supply voltage. Upon the simulation results, the proposed DLL operates correctly from 200MHz to 800MHz. The power consumption is less than 24mW at 800MHz. The active area of the design is 0.178mm/sub 2/.